Typically, as illustrated in FIG. 1, an Embedded System 122 comprises a Central Processing Unit (CPU) 130, Memory 132, Bus Interface 126, peripherals 120, controllers 124 and Debug Unit 128. The peripherals 120 herein refer to one or more hardware ports with a communication protocol such as a Universal Asynchronous Receiver Transmitter (UART), Universal Serial Bus (USB), Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I2C), Secure Digital Input Output (SDIO), Wireless Local area network (WLAN), Bluetooth (BT), Infrared (IR), etc. The Debug Unit 128 is tightly coupled with CPU 130 in the Embedded System 122. The CPU is also referred to as a processor herein. The Embedded System 122 may contain other software or hardware components which are not shown in the FIG. 1.
As illustrated in FIG. 1, a debugger 112 refers to the device with controller unit 114, standard Joint Test Action Group (JTAG) Physical Interface 116 and USB Device Interface 110. The debugger 112 may be usually a specialized hardware device.
The Host Computer 102 comprises JTAG USB Debugger Software 104, Operating System (OS) 134, USB Interface Driver 106 and USB Host Interface 108. The Host Computer 102 may contain other hardware or software components which are not shown in the FIG. 1. An operating system (OS) 134 is system software that manages Host Computer hardware and software resources and provides common services for computer programs.
The Debugger 112 is connected with the Embedded System 122 using the dedicated JTAG physical cable 118. The USB Host Interface 108 of the Host Computer 102 and the USB device interface 110 of the Debugger 112 are connected through the physical USB cable 136.
As shown in FIG. 2, an Executable Binary 202 comprises Program, Global symbols information and Debug Section packed as described in Debugging With Attributed Record Formats (DWARF), DWARF Debugging Information Format Committee, Jun. 10, 2010, pp. 1-6, incorporated by reference herein. DWARF is a debugging format used to describe programs. The Executable Binary 202 may follow standard formats such as Executable and Linkable format (ELF). The ELF refers to the whole Executable Binary 202 whereas the DWARF refers to Debug Section 208 alone. The Debug Section 208 of the Executable Binary 202 may also contain additional information which is not shown in the FIG. 2. The Program 204 refers to the set of instructions to control the behavior of the Embedded System 122. The Global symbols information 206 refers to the symbol names used in the Program 204 pointing to a particular address in the Memory 132 of the Embedded System 122. The Global symbols are also referred to as the Global variables and the two terms are used interchangeably herein.
The Debug Section 208 comprises DBG_INFO 210 section and DBG_ABRV 212 section, containing the detailed attributes of Global symbols information 206. The DBG_INFO represents the contents of individual symbols whereas DBG_ABRV represents the attributes of each symbol. As per the DWARF specification, the Global symbols are packed into DBG_INFO and DBG_ABRV in consecutive block units termed as Compilation Unit (CU). Each of the symbols contains the “Data Type” information which indicates the number of bytes occupied by a symbol in Memory (storage) of the Embedded System. Each Data Type comprises one or more “Base Data Type” of different sizes.
Returning to FIG. 1, the JTAG USB Debugger Software 104 in the Host Computer 102 extracts the Program 204 from Executable Binary 202 and loads it into the Memory 132 of the Embedded System. The CPU 130 then executes the Program 204 from the Memory 132 of the Embedded System when powered up. The JTAG USB Debugger Software 104 controls the execution of the CPU 130 through the Debug Unit 128 and provides the symbol information in the Host Computer. Whenever the JTAG USB Debugger Software 104 is accessing the CPU 130, the CPU stops the execution of Program 204 and responds to the Host Computer commands and requests.
The term “Dynamic” herein refers to the capability of the Debugger to operate without halting the processor and “Global” refers to the capability to operate universally across all peripheral interfaces and processor types.
The interface between a Host Computer and the Embedded System is referred herein as “Host interface.” This may be USB, SDIO, UART, etc. As shown in FIG. 1, a typical Debugger device is connected to a Host Computer using the host interface. The Debugger comprises a controller unit which transfers the data between USB and JTAG interface. The JTAG interface is physically connected to the Debug Unit in the Embedded System. The Debug Unit is coupled with the CPU in the Embedded System. The CPU communicates with Memory, Peripherals and Controllers within the Embedded System through Bus Interface. A typical JTAG interface, for example, may use six pins. The Debug Unit coupled with the processor in the Embedded System controls the processor whenever the Host Computer tries to access it.